The present invention relates to the art for semiconductor integrated circuit and the art specifically effective for use in a clamp system for elevated voltage and an input latch system. More particularly, the present invention relates to the art effective for use in a voltage elevating circuit and a mode setting circuit for EEPROM (electrically erasable programmable read-only memory).
In an electrically writable and erasable EEPROM device using nonvolatile storage elements such as MNOS (metal nitride oxide semiconductor), a voltage Vpp (for example, +15 V) higher than the voltage used when reading (+5 V) is required for writing and erasing data. Such a high voltage may be supplied from outside the chip, but recently there has been proposed an EEPROM being provided therein with a voltage elevating circuit using a charge pump and a voltage limiting circuit using a clamp diode and thereby adapted to be driven by a single power supply (Japanese Laid-open Patent Publication No. 61-24094). The purpose of this arrangement is to decrease the number of the external circuits and thereby to relieve users work load.
In an EEPROM apparatus, such tests are sometimes performed as measurement of the write voltage margin by weak writing, with a lower write voltage Vpp than usual, and a high-voltage test by strong writing, with a higher write voltage Vpp than usual, as well as an accelerated test by such strong writing to find permissible number of times of rewriting.
However, the EEPROM apparatus having the voltage elevating circuit provided within its chip as aforesaid has no Vpp terminal, and it is therefore impossible to apply a write voltage Vpp at a desired magnitude from outside. Hence, such tests by means of weak writing or strong writing are impracticable.
When the object of the testing is in the stage of a wafer, it can be managed to perform such tests by providing suitable pads on the chip and using probes. But, after the chip has been sealed in a package, it becomes impossible.
Generally, a 64k-bit EEPROM has 28 pins, of which the first and 26th pins are normally idle. Hence, there is proposed an EEPROM adapted to function in a test mode when a test control signal is input thereto using the idle pins. Such an art is disclosed, for example, in "Nikkei Electronics", published on Oct. 21, 1985, pp. 127-154.
In case of a 256k-bit EEPROM, however, since two pins are additionally required as address signal input pins, the generally provided 28 pins as they are not sufficient for establishing the test mode. Therefore, not only a test mode but also another operating mode becomes difficult to be added.
In order to set up a mode without increasing the number of pins but utilizing an existing control terminal, such an EEPROM is also proposed wherein the setting up of a test mode or the like is achieved by adapting the control terminal to be an input terminal for three levels.
When an input terminal for three levels is provided, however, it becomes difficult to set up two threshold values. Hence, there occur such problems that the threshold values varies according to processes and level setting of an external signal becomes troublesome.
In semiconductor memory, it has been in general practice to have operating modes established by combination of such signals as a chip enable signal CE and a write enable signal WE. Also in an EEPROM, modes have been established by combination of a chip enable signal CE, write enable signal WE, and an output enable signal OE.
When establishing these modes by the use of the three terminals as aforesaid, it may be possible to establish 2.sup.3 or 8 modes. In reality, however, when the chip enable signal CE is at HIGH level, the chip as a whole is put into a standby mode. Hence, all its combinations with other control signals become ineffective. Therefore, it follows that only five modes can be established including the standby mode. Since these modes are almost used up for necessary modes for the EEPROM such as a write mode, read mode, and a write inhibit mode, it has been difficult to add new test mode or the like without increasing the number of pins.